1. Field
The present disclosure relates generally to a layout construction, and more particularly, to an adaptive standard cell architecture and layout techniques for low area digital system-on-chip (SoC).
2. Background
A standard cell is an integrated circuit that may be implemented with digital logic. An application-specific integrated circuit (ASIC), such as an SoC device, may contain thousands to millions of standard cells. Such standard cells may occupy around 20% of an SoC. Reducing a size/area footprint of ASICs is beneficial. Accordingly, there is a need for reducing the size/area footprint of individual standard cells.